A Commodore Pet in an FPGA

September, 2011



I miss my old Commodore Pet. It was a blue-face with the chiclet-style keyboard. So, I'm recreating it in a Xilinx Spartan-6 FPGA. I'm using a Digilent Nexys3 development board. The design runs original version 1 or 2 ROMs.

Features:

The FPGA is clocked at 100Mhz 50Mhz. I use a divide by 100 50 counter to create a "slow clock" to pace the 6502 and to drive the 6522 VIA's timers. Toggling switch 0 allows the 6502 to go full speed (i.e. 50Mhz). (See my Dec 14, 2011 notes below on why I'm now running at 50Mhz.)

The video is 640x400 @ 60hz VGA. The PET has x 320x200 screen so each pixel is double wide and double tall. I've implemented the screen blanking function even though there's no "snow" when writing to video RAM.


September 30, 2011: it's coming along. I've rigged up a PS/2 connector to the Nexys3 for keyboard input. I've come up with a somewhat useful mapping from the PC keyboard to the 10x8 PET keyboard. FPGA hardware does the mapping.

October 6, 2011: It's now able to load programs from cassette! A raw binary image of a cassette is sent over RS-232 at 38,400 baud and the PET loads it just like a tape (as slow as one too). A couple PERL scripts convert .TAP files into the raw binary data and I managed to load Space Invaders! It's not working exactly right (maybe it got corrupted) but check it out!

October 16, 2011: I finally got some time to putter with this. The problem with Space Invaders went away when I "upgraded" to second generation ROMs. I think the first ROMs had a conflict with a zero-page location Space Invaders was using (0xFB/0xFC).

October 24, 2011: A first release of the source: pet2001fpga-0.1.tgz

November 11, 2011: I got the idea to create a composite video interface because it seems even new HDTVs still have composite video in. See picture at bottom of page.

December 14, 2011: I've revamped the CPU so that it no longer has an enable signal and is better pipelined so most cycles are used for reading and writing. It can still clock at 100Mhz but the Spartan memories have a latch on the address so reads would still take two cycles. To better test my 6502 with no wait states, I've halved the clock to 50Mhz and I run the memories on falling edge of the clock (in other words, I still only have 10ns to generate the address but I get the data in the same cycle). I'm basically getting the same performance at half the clock speed.

December 15, 2011: Here's the latest source: pet2001fpga-0.3.2.tgz.

January 11, 2012: Just a note, I got this working on a Spartan 3AN Starter Board development board as well. Drop me an email if you're interested.

January 20, 2013: Put the source back here: pet2001fpga-0.4.1.tgz. I'm thinking of putting this on github but for now it's back here.


Space Invaders:

Fire! (From Cursor magazine)

Checkers! A program I published in Cursor Magazine way back in 1980:

Breakout:

Composite output on a 42" display:



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