Yet Another Apple2+ in an FPGA

August 29, 2007

I've recreated my old Apple ][+ in an FPGA. I know it's been done before but I got this Spartan 3AN Starter Board a few weeks ago and I needed a project to get used to the tools and to dust off my Verilog and FPGA skills.

Features:

The 6502 is clocked at 50 Mhz. In an Apple ][ it runs at 1Mhz. My implementation has an extra execute cycle and a wait state for synchronous memory reads so it runs about 20 times as fast as a normal Apple 2. I've also added an optional 20 cycle wait state generator (enabled by one of the toggle switches) to slow down the processer so it will act more like a normal Apple (otherwise the "beep" becomes a "click").




I wouldn't have been able to do it if I hadn't saved this reference manual through countless moves.


E-mail Me